Analysis and Characterization of Ultra Low Power Branch Predictors, A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, S. Ganapathy, J. Kalamatianos, IEEE International Conference on Computer Design (ICCD 2018), Orlando, Florida, USA, October 2018.
Energy Efficient Computing in Multicore CPUs: Design Margins and Variability Sunday, October 21 2018, Fukuoka, Japan Afternoon tutorial held in conjunction with 51st IEEE/ACM International Symposium on Microarchitecture (MICRO 2018) Organizers/Presenters: Dimitris Gizopoulos, George Papadimitriou, Athanasios Chatzidimitriou (University of Athens) Tutorial Summary Conservative design margins in modern multicore CPU chips aim to guarantee correct...
A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, “HealthLog Monitor: A Flexible System-Monitoring Linux Service, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), Costa Brava, Spain, July 2018. K. Tovletoglou, L. Mukhanov, G. Karakonstantis, A. Chatzidimitriou, G. Papadimitriou, M. Kaliorakis, D. Gizopoulos, Z. Hadjilambrou, Y. Sazeides, A. Lampropulos, S. Das, P. Vo,...
Energy Efficient Computing in Multicore CPUs: Design Margins and Variability Sunday, 3 June 2018, Los Angeles, California, USA Morning tutorial held in conjunction with 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018) Organizers/Presenters: Dimitris Gizopoulos, George Papadimitriou, Athanasios Chatzidimitriou (University of Athens) Tutorial Summary Conservative design margins in modern multicore CPU chips aim...
“Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs”, G. Papadimitriou, A. Chatzidimitriou, M. Kaliorakis, Y. Vastakis, D. Gizopoulos, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2018), Belfast, Northern Ireland, United Kingdom, April 2018.
“Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions”, M. Kaliorakis, A. Chatzidimitriou, G. Papadimitriou, and D. Gizopoulos, IEEE Computer Architecture Letters (CAL 2018), Volume: XX, Issue: X, pp. 0-0, February 2018.
Microarchitecture Level Reliability Assessment: Throughput and Accuracy Sunday, 15 October 2017, Boston, MA, USA Morning tutorial held in conjunction with MICRO 2017 Tutorial Summary Early assessment of the vulnerability of microprocessor components to hardware faults can drive effective protection decisions. Microarchitecture-level simulators are employed for such early assessments and can deliver reliability reports for...
“Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs”, G.Papadimitriou, M.Kaliorakis, A.Chatzidimitriou, D.Gizopoulos, P.Lawthers, S.Das, IEEE/ACM International Symposium on Microarchitecture (MICRO 2017), Boston, MA, USA, October 2017.
“RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU”, A.Chatzidimitriou, M.Kaliorakis, D.Gizopoulos, M.Iacaruso, M.Pipponzi, R.Mariani, S.Di Carlo, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), Denver, CO, USA, June 2017.
“MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment”, M.Kaliorakis, D.Gizopoulos, R.Canal, A.Gonzalez, ACM/IEEE International Symposium on Computer Architecture (ISCA 2017), Toronto, Canada, June 2017