Publication List

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2024

O. Chatzopoulos, G. Papadimitriou, V. Karakostas, and D. Gizopoulos, “gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures”, IEEE International Symposium on High-Performance Computer Architecture (HPCA 2024), Edinburgh, Scotland, March 2024.

2023

D. Agiakatsikas, G. Papadimitriou, V. Karakostas, D. Gizopoulos, M. Psarakis, C. Belanger-Champagne, and E. Blackmore, “Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs”, IEEE/ACM International Symposium on Microarchitecture (MICRO 2023), Toronto, Canada, October 2023.

R. Canal, C. Chenet, A. Arelakis, J. M. Arnau, J. L. Berral, A. Call, S. Di Carlo, J. Costa, D. Gizopoulos, V. Karakostas, F. Lubrano, K. Nikas, Y. Nikolakopoulos, B. Otero, G. Papadimitriou, I. Papaefstathiou, D. Pnevmatikatos, D. Raho, A. Rigo, E. Rodríguez, A. Savino, A. Scionti, N. Tampouratzis, and A. Torregrosa, “Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services”, Euromicro Conference Series on Digital System Design (DSD 2023), Durres, Albania, September 2023.

P. Bodmann, G. Papadimitriou, R. L. Rech Jr, D. Gizopoulos, and P. Rech, “Soft Error Effects on Arm Microprocessors: Early Estimations Versus Chip Measurements”, IEEE Transactions on Computers (IEEE TC), Volume: 56, Issue: 7, pp. 4-6, July 2023.

G. Papadimitriou, D. Gizopoulos, H. D. Dixit, and S. Sankar, “Silent Data Corruptions: The Stealthy Saboteurs of Digital Integrity”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2023), Crete, Greece, July 2023.

G. Papadimitriou and D. Gizopoulos, “Silent Data Corruptions: Microarchitectural Perspectives”, IEEE Transactions on Computers (IEEE TC), June 2023.

G. Papadimitriou and D. Gizopoulos, “Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers”, IEEE Transactions on Emerging Topics in Computing (IEEE TETC), Volume: 11, Issue: 2, pp. 420-431, April-June 2023.

M. Alonso, D. Andreu, R. Canal, S. Di Carlo, C. Chenet, J. Costa, A. Girones, D. Gizopoulos, V. Karakostas, B. Otero, G. Papadimitriou, E. Rodrıguez, and A. Savino, “Validation, Verification, and Testing (VVT) of Future RISC-V Powered Cloud Infrastructures: the Vitamin-V Horizon Europe Project Perspective”, IEEE European Test Symposium (ETS 2023), Venice, Italy, May 2023.

F. Pavanello, C. Marchand, I. O’Connor, R. Orobtchouk, F. Mandorlo, X. Letartre, S. Cueff, E. Vatajelu, G. Di Natale, B. Cluzel, A. Coillet, B. Charbonnier, P. Noé, F. Kavan, M. Zoldak, M. Szaj, P. Bienstman, T. Van Vaerenbergh, U. Ruhrmair, P. Flores, L. Guerra e Silva, R. Chaves, L. M. Silveira, M. Ceccato, D. Gizopoulos, G. Papadimitriou, V. Karakostas, A. Brando, F. J. Cazorla, R. Canal, P. Closas, A. Gusi-Amigo, P. Crovetti, A. Carpegna, T. Melendez Carmona, S. Di Carlo, and A. Savino, “NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS”, IEEE European Test Symposium (ETS 2023), Venice, Italy, May 2023.

A. Singh, S. Chakravarty, G. Papadimitriou, and D. Gizopoulos, “Silent Data Errors: Sources, Detection, and Modeling”, IEEE VLSI Test Symposium (VTS 2023), San Diego, CA, USA, April 2023.

G. Papadimitriou and D. Gizopoulos, “AVGI: Microarchitecture-Driven, Fast and Accurate Vulnerability Assessment”, IEEE International Symposium on High-Performance Computer Architecture (HPCA 2023), Montreal, QC, Canada, February 2023.

 

2022

G. Papadimitriou and D. Gizopoulos, “Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers”, IEEE Transactions on Emerging Topics in Computing (IEEE TETC), September 2022.   

Y. Sazeides, A. Gerber, R. Gabor, A. Bramnik, G. Papadimitriou, D. Gizopoulos, C. Nicopoulos, G. Dimitrakopoulos, and K. Patsidis, “IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming”, ACM/IEEE International Symposium on Microarchitecture (MICRO 2022), Chicago, Illinois, USA, October 1-5, 2022.   

C. Alverti, V. Karakostas, N. Kunati, G. Goumas, and M. Swift, “DaxVM: Stressing the Limits of Memory as a File Interface”, ACM/IEEE International Symposium on Microarchitecture (MICRO 2022), Chicago, Illinois, USA, October 1-5, 2022.

P. R. Bodmann, G. Papadimitriou, R. L. Rech Jr, D. Gizopoulos, and P. Rech, “Soft Error Effects on Arm Microprocessors: Early Estimations vs. Chip Measurements”, IEEE Transactions on Computers (IEEE TC), Volume: 71, Issue: 10, pp. 2358-2369, October 2022.   

D. Sartzetakis, G. Papadimitriou, and D. Gizopoulos, “gpuFI-4: A Microarchitecture-Level Framework for Assessing the Cross-Layer Resilience of Nvidia GPUs”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2022), Singapore, May 2022.   
[Best Paper Candidate]   

 

2021

G. Papadimitriou, and D. Gizopoulos, “Characterizing Soft Error Vulnerability of CPUs Across Compiler Optimizations and Microarchitectures”, IEEE International Symposium on Workload Characterization (IISWC 2021), Virtual Online Event, November 2021.   

I. Tsiokanos, G. Papadimitriou, D. Gizopoulos, and G. Karakonstantis, “Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors”, IEEE International Symposium on Workload Characterization (IISWC 2021), Virtual Online Event, November 2021.   

G. Papadimitriou, and D. Gizopoulos, “Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers”, IEEE/ACM International Symposium on Computer Architecture (ISCA 2021), Virtual Event, June 2021.   

O. Chatzopoulos, G. Fragkoulis, G. Papadimitriou, and D. Gizopoulos, “Towards Accurate Performance Modeling of RISC-V Designs”, Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), Virtual Event, June 2021.   

Pablo Bodmann, G. Papadimitriou, D. Gizopoulos, and P. Rech, “The Impact of SoC Integration and OS Deployment on the Reliability of Arm Processors”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2021), Virtual On-Line Meeting, March 2021.   

 

2020

P. Koutsovasilis, C. Antonopoulos, N. Bellas, S. Lalis, G. Papadimitriou, A. Chatzidimitriou, and D. Gizopoulos, “The Impact of CPU Voltage Margins on Power-Constrained Execution”, IEEE Transactions on Sustainable Computing (IEEE TSUSC), December 2020.   

P. Bodnmann, G. Papadimitriou, D. Gizopoulos, and P. Rech, “Impact of Cores Integration and Operating System on ARM Processors Reliability: Micro-Architectural Fault-Injection vs Beam Experiments”, IEEE European Conference on Radiation and Its Effects on Components and Systems (RADECS 2020), Virtual Online Event, October 2020.

G. Papadimitriou, A. Chatzidimitriou, D. Gizopoulos, V. J. Reddi, J. Leng, B. Salami, O. S. Unsal, and A. C. Kestelman, “Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins”, IEEE Transactions on Device and Materials Reliability (IEEE TDMR), Volume: 20, Issue: 2, pp. 341-350, June 2020.   

A. Chatzidimitriou and D. Gizopoulos, “RACE: Reverse-Order Processor Reliability Analysis”, Design, Automation and Test in Europe Conference (DATE 2020), Grenoble, France, March 2020.   

 

2019

A. Chatzidimitriou, G. Papadimitriou, C. Gavanas, G. Katsoridas, and D. Gizopoulos, “Multi-Bit Upsets Vulnerability Analysis of Modern Microprocessors”, IEEE International Symposium on Workload Characterization (IISWC 2019), Orlando, Florida, USA, November 2019.   

D. Gizopoulos, G. Papadimitriou, A. Chatzidimitriou, V. J. Reddi, J. Leng, B. Salami, O. S. Unsal, and A. C. Kestelman, “Modern Hardware Margins: CPUs, GPUs, FPGAs”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2019), Rhodes Island, Greece, July 2019.   

A. Chatzidimitriou, P. Bodmann, G. Papadimitriou, D. Gizopoulos, and P. Rech, “Demystifying Soft Error Assessment Strategies on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam Experiments”, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019), Portland, Oregon, USA, June 2019.   
[Best Paper Award Nomination]   

P. Nikolaou, Y. Sazeides, A. Lampropulos, D. Guilhot, A. Bartoli, G. Papadimitriou, A. Chatzidimitriou, D. Gizopoulos, K. Tovletoglou, L. Mukhanov, and G. Karakonstantis, “On the Evaluation of the Total-Cost-of-Ownership Trade-offs in Edge vs Cloud deployments: A Wireless-Denial-of-Service Case Study”, IEEE Transactions on Sustainable Computing (IEEE T-SUSC), 2019.   

A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, S. Ganapathy, and J. Kalamatianos, “Assessing the Effects of Low Voltage in Branch Prediction Units”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2019), Madison, Wisconsin, USA, March 2019.   

A. Chatzidimitriou, G. Papadimitriou, and D. Gizopoulos, “HealthLog Monitor: Errors, Symptoms and Reactions Consolidated”, IEEE Transactions on Device and Materials Reliability (IEEE TDMR), Vol.: 19, Issue: 1, pp. 46-54, March 2019.   

G. Papadimitriou, A. Chatzidimitriou, and D. Gizopoulos, “Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs”, IEEE International Symposium on High-Performance Computer Architecture (HPCA 2019), Washington D.C., USA, February 2019.   

 

2018

A. Vallero et al., “SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems”, IEEE Transactions on Computers (IEEE TOC), Vol. 68, no. 5, pp. 765–783, May 2019.   

A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, S. Ganapathy, J. Kalamatianos, “Analysis and Characterization of Ultra Low Power Branch Predictors”, IEEE International Conference on Computer Design (ICCD 2018), Orlando, Florida, USA, October 2018.   

A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, “HealthLog Monitor: A Flexible System-Monitoring Linux Service”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), Costa Brava, Spain, July 2018.   

M. Kaliorakis, A. Chatzidimitriou, G. Papadimitriou, and D. Gizopoulos, “Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions”, IEEE Computer Architecture Letters (IEEE CAL), Volume: 17, Issue: 2, pp. 109-112, July 2018.   

K. Tovletoglou, L. Mukhanov, G. Karakonstantis, A. Chatzidimitriou, G. Papadimitriou, M. Kaliorakis, D. Gizopoulos, Z. Hadjilambrou, Y. Sazeides, A. Lampropulos, S. Das, P. Vo, “Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs”, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2018), Luxembourg, June 2018.   

A. Vallero, S. Tselonis, D. Gizopoulos, S. Di Carlo, “Multi-faceted Microarchitecture Level Reliability Characterization for NVIDIA and AMD GPUs”, IEEE VLSI Test Symposium (VTS 2018), San Fransisco, California, USA, April 2018.   

G. Papadimitriou, A. Chatzidimitriou, M. Kaliorakis, Y. Vastakis, D. Gizopoulos, “Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2018), Belfast, Northern Ireland, United Kingdom, April 2018.   

G. Karakonstantis, K. Tovletoglou, L. Mukhanov, H. Vandierendonck, D. S. Nikolopoulos, P. Lawthers, P. Koutsovasilis, M. Maroudas, C. D. Antonopoulos, C. Kalogirou, N. Bellas, S. Lalis, S. Venugopal, A. Prat-Perez, A. Lampropulos, M. Kleanthous, A. Diavastos, Z. Hadjilambrou, P. Nikolaou, Y. Sazeides, P. Trancoso, G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, and S. Das, “An Energy-Efficient and Error-Resilient Server Ecosystem Exceeding Conservative Scaling Limits”, ACM/IEEE Design, Automation, and Test in Europe (DATE 2018), Dresden, Germany, March 2018.   

 

2017

G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, P. Lawthers, and S. Das, “Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs”, IEEE/ACM International Symposium on Microarchitecture (MICRO 2017), Boston, MA, USA, October 2017.   

G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, C. Magdalinos, D. Gizopoulos, “Voltage Margins Identification on Commercial x86-64 Multicore Microprocessors”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, July 2017.   

A. Vallero, S. Di Carlo, D. Gizopoulos, “SIFI: AMD Southern Island GPU Microarchitectural Level Fault Injector”,  IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, July 2017.   

A.Chatzidimitriou, M.Kaliorakis, D.Gizopoulos, M.Iacaruso, M.Pipponzi, R.Mariani, S.Di Carlo, “RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU”, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), Denver, CO, USA, June 2017.   

M. Kaliorakis, D. Gizopoulos, R. Canal, A. Gonzalez, “ MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment”, ACM/IEEE International Symposium on Computer Architecture (ISCA 2017), Toronto, Canada, June 2017.   

A. Chatzidimitriou, M. Kaliorakis, S. Tselonis, D. Gizopoulos, “Performance-Aware Reliability Assessment of Heterogeneous Chips”, IEEE VLSI Test Symposium (VTS 2017), Las Vegas, NV, USA, April, 2017.   

G. Papadimitriou, D. Gizopoulos, A. Chatzidimitriou, and R. Morad “An Agile Post-Silicon Validation Methodology for the Address Translation Mechanisms of Modern Microprocessors”, IEEE Transactions on Device and Materials Reliability (TDMR 2017), Volume: 17, Issue: 1, pp. 3-11, March 2017.   

A. Vallero, S. Tselonis, S. Di Carlo, D. Gizopoulos, “Microarchitecture Level Reliability Comparison of Modern GPU Designs: First Findings”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2017), 2017 (poster in the formal IEEE proceedings)   

G. Karakonstantis, K. Tovletoglou, L. Mukhanov, H. Vandierendonck, D. S. Nikolopoulos, P. Koutsovasilis, C. Antonopoulos, A. Prat, M. M. Rafique, S. Venugopal, A. Diavastos, Z. Hadjilambrou, P. Nikolaou, Y. Sazeides, P. Trancoso, G. Papadimitriou, M. Kaliorakis, A. Chatzidimitriou, D. Gizopoulos, “An Energy-Efficient and Error-Resilient Server Ecosystem Exceeding Conservative Scaling Limits”, in Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), Stockholm, Sweden, co-located with HiPEAC 2017.

 

2016

A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D.  Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio, G. Di Natale, “Cross-Layer System Reliability Assessment Against Hardware Faults”, IEEE International Test Conference (ITC 2016), November 2016.   

G. Papadimitriou, D. Gizopoulos, A. Chatzidimitriou, T. Kolan, A. Koyfman, R. Morad and V. Sokhin, “Unveiling Difficult Bugs in Address Translation Caching Arrays for Effective Post-Silicon Validation”, IEEE International Conference on Computer Design (ICCD 2016), Phoenix, AZ, USA, October 2016.   

A. Pavlidis, D. Gizopoulos, “Hierarchical Synthesis of Quantum and Reversible Architectures“, Springer, International Journal of Parallel Programming (IJPP 2016), vol. 44, no. 5, pp. 1028-1053, October 2016.   

G. Papadimitriou, A. Chatzidimitriou, D. Gizopoulos and R. Morad, “ISA-Independent Post-Silicon Validation for the Address Translation Mechanisms of Modern Microprocessors”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), Sant Feliu de Guixols, Spain, July 2016. [ranked #1 ]   

S. Di Carlo, A. Savino, A. Vallero, G. Politano, D. Gizopoulos, A. Evans, “RIIF-2: toward the next generation Reliability Information Interchange Format”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2016), July 2016.   

S. Tselonis, M. Kaliorakis, N. Foutris, G. Papadimitriou and D. Gizopoulos, “Microprocessor Reliability-Performance Tradeoffs Assessment at the Microarchitecture Level”, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April 2016.   

A. Chatzidimitriou, D. Gizopoulos, “Anatomy of Microarchitecture-Level Reliability Assessment: Throughput and Accuracy”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2016), Uppsala, Sweden, April, 2016.   

S. Tselonis, D. Gizopoulos, “GUFI: a Framework for GPUs Reliability Assessment”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2016), Uppsala, Sweden, April, 2016.   

S. Tselonis, M. Kaliorakis, N. Foutris, G. Papadimitriou, D. Gizopoulos, “Microprocessor Reliability-Performance Tradeoffs Assessment at the Microarchitecture Level”, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.   

N. Foutris, A. Chatzidimitriou, D. Gizopoulos, J. Kalamatianos, V. Sridharan, “Faults in Data Prefetchers: Performance Degradation and Variability”, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.   

G.Papadimitriou, A.Chatzidimitriou, D.Gizopoulos, R.Morad, “Accelerating Post-Silicon Validation for the Address Translation Mechanisms of Modern Microprocessors”, ACM/IEEE Design Automation Conference (DAC 2016), June 2016. (poster; no proceedings).

A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio, G. Di Natale, “Early Component-Based System Reliability Analysis for Approximate Computing Systems”, 2^nd HiPEAC Workshop on Approximate Computing (WAPCO 2016), Prague, Czech Republic, January 18-20, 2016 (paper in informal proceedings).

 

2015

A. Vallero, S. Tselonis, N. Foutris, M. Kaliorakis, M. Kooli, A. Savino, G. Politano, A. Bosio, G. Di Natale, D. Gizopoulos, S. Di Carlo, “Cross-Layer Reliability Evaluation, moving from the Hardware Architecture to the System level”, Elsevier, Microprocessors and Microsystems, vol. 39, no. 8, pp. 1204-1214, November 2015.    

M. Kaliorakis, S. Tselonis, A. Chatzidimitriou, N. Foutris, D. Gizopoulos, “Differential Fault Injection on Microarchitectural Simulators”, IEEE International Symposium on Workload Characterization (IISWC 2015), Atlanta, GA, USA, October 2015.     

M. Kaliorakis, S. Tselonis, A. Chatzidimitriou, D. Gizopoulos, “Accelerated Microarchitectural Fault Injection-Based Reliability Assessment”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 2015), Amherst, MA, USA, October 2015. [best paper award candidate]   

A. Keliris, O. Kremmyda, V. Dimitsas, M. Maniatakos, D. Gizopoulos, “Efficient Parallelization of the Discrete Wavelet Transform Algorithm using Memory-oblivious Optimizations”, IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2015), Salvador, Bahia, Brazil, September 2015. [best paper award].   

A. Vallero, A. Savino, G. Politano, S. Di Carlo, S. Tselonis, M. Kaliorakis, N. Foutris, D. Gizopoulos, “Bayesian Network Early Reliability Evaluation Analysis for both Permanent and Transient Faults”, IEEE International On-Line Testing Symposium (IOLTS 2015), July 2015.   

A. Pavlidis and D. Gizopoulos, “Hierarchical Synthesis of Quantum and Reversible Architectures”, ACM International Conference on Computing Frontiers (CF 2015), Ischia, Italy, May 2015. [best paper award candidate]   

M. Ottavi, S. Pontarelli, D. Gizopoulos, et al, “Dependable Multicore Architectures at Nanoscale and their Applications“, IEEE Design & Test of Computers Magazine, vol. 32, no. 2, pp. 17-28, April 2015.     

A. Vallero, S. Di Carlo, A. Savino, D. Gizopoulos, M. Kaliorakis, S. Tselonis, N. Foutris, G. Politano, “A Bayesian model for System Level Reliability Estimation”, IEEE European Test Symposium (ETS 2015), Cluj-Napoca, Romania, May 2015 (poster in formal IEEE proceedings).    

V. Dimitsas, O. Kremmyda, D. Gizopoulos, A. Keliris, M. Maniatakos, “Implementation and Evaluation of DWT on Contemporary NVIDIA GPUs and x86 CPUs”, 2015 GPU Technology Conference (GTC 2015), Nvidia, San Jose, CA, USA, March 17-20, 2015.

 

2014

A. Pavlidis, D. Gizopoulos, “Fast Quantum Modular Exponentiation Architecture for Shor’s Factorization Algorithm”, Quantum Information and Computation (QIC), vol. 14, no. 7&8, pp. 649-682, May 2014.    

S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Grasset, R. Mariani, F. Reichenbach, X. Vera, “Cross-Layer Early Reliability Evaluation for the Computing Continuum”, Euromicro Conference on Digital System Design (DSD 2014), Verona, Italy, August 2014.     

N. Foutris, M. Kaliorakis, S. Tselonis, D. Gizopoulos, “Versatile Architecture-Level Fault Injection Framework for Early Reliability Evaluation”, IEEE On-Line Testing Symposium (IOLTS 2014), Platja d’Aro, Spain, July 2014.    

G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “Power-Aware Optimization of Software-Based Self-Test for L1 Caches in Microprocessors”, IEEE On-Line Testing Symposium (IOLTS 2014), Platja d’Aro, Spain, July 2014.    

M. Kaliorakis, M. Psarakis, N. Foutris, D. Gizopoulos, “Accelerated Online Error Detection in Many-core Microprocessor Architectures”, IEEE VLSI Test Symposium (VTS 2014), Napa, CA, USA, April, 2014.    

S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Gonzalez, R. Canal, R. Mariani, M. Pipponzi, A. Grasset, P. Bonnot, F. Reichenbach, G. Rafiq, T. Loekstad, “Cross-Layer Early Reliability Evaluation: Challenges and Promises”, IEEE International On-Line Testing Symposium (IOLTS 2014), Platja d’Aro, Spain, July 2014.    

M. Kaliorakis, M. Psarakis, N. Foutris, D. Gizopoulos, “Parallelizing Online Error Detection in Many-core Microprocessor Architectures”, HiPEAC Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and Transactional Memory Systems, Vienna, Austria, January 2014. (full paper review; informal proceedings)

2013

G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “A Software-Based Self-Test Methodology for On-Line Testing of Processor L1 Caches”, IEEE Transactions on VLSI Systems (TVLSI), vol. 21, no. 4, pp. 786-790, April 2013.    

N. Foutris, D. Gizopoulos, J. Kalamatianos, V. Sridharan, “Assessing the Impact of Hard Faults in Performance Components of Modern Microprocessors”, IEEE International Conference on Computer Design (ICCD 2013), Asheville, NC, USA, October 2013.    

N. Foutris, D. Gizopoulos, X. Vera, A. Gonzalez, “Deconfigurable Microprocessor Architectures for Silicon Debug Acceleration”, ACM/IEEE International Symposium on Computer Architecture (ISCA 2013), Tel-Aviv, Israel, June 2013.    

S. Tselonis, V. Dimitsas, D. Gizopoulos, “The Functional and Performance Tolerance of GPUs to Permanent Faults in Registers”, IEEE International On-Line Testing Symposium (IOLTS 2013), Chania, Greece, July 2013.    

M. Kaliorakis, N. Foutris, D. Gizopoulos, M. Psarakis, “Online Error Detection in Multiprocessor Chips: A Test Scheduling Study”, IEEE International On-Line Testing Symposium (IOLTS 2013), Chania, Greece, July 2013. (full paper review; poster in formal proceedings)     

S. Hamdioui, D. Gizopoulos, G. Guido, M. Nicolaidis, A. Grasset, P. Bonnot, “Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes”, ACM/IEEE Design, Automation, and Test in Europe Conference (DATE 2013), Grenoble, France, April 2013.    

A. Sari, M. Psarakis, D. Gizopoulos, “Combining Checkpointing and Scrubbing in FPGA-based Real-Time Systems”, IEEE VLSI Test Symposium (VTS 2013), Berkeley, CA, USA, May, 2013.    

 

2012

N. Axelos, K. Pekmestzi, D. Gizopoulos, “Efficient Memory Repair Using Cache-Based Redundancy”, IEEE Transactions on VLSI Systems (TVLSI), vol. 20, no. 12, pp. 2278-2288, December 2012.    

A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Low Energy On-Line Self-Test of Embedded Processors in Dependable WSN Nodes”, IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 9, no. 1, pp. 86-100, January/February 2012.    

A. Paschalis, I. Voyiatzis, D. Gizopoulos, “Accumulator based 3-Weight Pattern Generation”, IEEE Transactions on VLSI Systems (TVLSI), vol. 20, no. 2, pp. 357-361, February 2012.    

G. Theodorou, S. Chatzopoulos, N. Kranitis, A. Paschalis, D. Gizopoulos, “A Software-Based Self-Test Methodology for On-Line Testing of Data TLBs”, IEEE European Test Symposium (ETS 2012), Annecy, France, May 2012. (full paper review; poster in formal proceedings).    

G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “On-Line Software-Based Self-Test for Data TLBs”, International Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012), Annecy, France, June, 2012. (full paper review; informal proceedings).

 

2011

J. Collet, P. Zajac, M. Psarakis, D. Gizopoulos, “Chip Self-Organization and Fault-Tolerance in Massively Defective Multicore Arrays”, IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 8, no. 2, pp. 207-217, March-April 2011.    

N. Foutris, D. Gizopoulos, M. Psarakis, X. Vera, A. Gonzalez, “Accelerating Microprocessor Silicon Validation by Exposing ISA Diversity”, ACM/IEEE 44^th International Symposium on Microarchitecture (MICRO 2011), Porto Alegre, Brazil, December 2011.    

J. Abella, F. J. Cazorla, E. Quinones, D. Gizopoulos, A. Grasset, S. Yehia, P. Bonnot, R. Mariani, G. Bernat, “Towards Improved Survivability in Safety-Critical Systems”, IEEE International On-Line Testing Symposium (IOLTS 2011), Athens, Greece, July 2011.

G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, IEEE International Test Conference (ITC 2011), Anaheim, California, USA, September 2011.    

D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, X. Vera, “Architectures for Online Error Detection and Recovery in Multicore Processors”, ACM/IEEE Design, Automation, and Test in Europe Conference (DATE 2011), Grenoble, France, April 2011.

 

2010

M. Psarakis, D. Gizopoulos, E. Sanchez, M. Sonza Reorda, “Microprocessors Software-Based Self-Testing”, IEEE Design & Test of Computers Magazine (D&T), vol. 27, no. 3, pp. 4-19, May-June 2010.    

I. Voyiatzis, D. Gizopoulos, A. Paschalis, “Recursive Pseudo-Exhaustive Two-pattern Generation”, IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 1, pp. 142-152, January 2010.    

A. Merentitis, A. Paschalis, D. Gizopoulos, N. Kranitis, “Energy-Optimal On-Line Self-Test of Microprocessors in WSN Nodes”, IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, The Netherlands, October 2010.    

N. Foutris, M. Psarakis, D. Gizopoulos, X. Vera, A. Gonzalez, “MT-SBST: Self-Test Optimization in Multithreaded Multicore Architectures”, IEEE International Test Conference (ITC 2010), Austin, Texas, USA, November 2010.    

G. Theodorou, N. Kranitis, A. Paschalis, D. Gizopoulos, “A Software-Based Self-Test Methodology for In-System Testing of Processor Cache Tag Arrays”, IEEE International On-Line Testing Symposium (IOLTS 2010), Corfu, Greece, July 2010.    

A. Merentitis, D. Margaris, N. Kranitis, A. Paschalis, D. Gizopoulos, “SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints”, IEEE International On-Line Testing Symposium (IOLTS 2010), Corfu, Greece, July 2010.    

 

2000 – 2009

 

1990 – 1999