Computer Architecture Lab
Dept. of Informatics & Telecommunications @ University of Athens
O. Chatzopoulos, G. Papadimitriou, V. Karakostas, and D. Gizopoulos, ”gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures”, IEEE International Symposium on High-Performance Computer Architecture (HPCA 2024), Edinburgh, Scotland, March 2024. P. Bodmann, G. Papadimitriou, R. L. Rech Jr, D. Gizopoulos, and P. Rech, “Soft Error Effects on Arm Microprocessors: Early Estimations vs. Chip Measurements”, IEEE Transactions on Computers (IEEE TC), Volume: 71, Issue: 10, pp. 2358-2369, October 2022. [2022 Best Paper Award from IEEE Transactions on Computers by the IEEE Computer Society Publications Board]
CAL focuses on different aspects of Computer Architecture. We deal with computing systems built around general-purpose and specialized CPUs, memory systems, and accelerators such as GPUs. We care about the complex interactions among different parameters including performance, power/energy and dependability/reliability. We deliver methods and tools for fast evaluation of reliability, for energy-efficient computing, for error detection and recovery, as well as for silicon debug and validation.
We design mechanisms for improving the performance of computing systems, focusing on emerging application domains that stress the limits of the memory system and its impact on execution. Our hardware, software, and co-design approach involves all the layers of the computing stack, from the application, the runtime and the OS, to the architecture and microarchitecture layers.
We devise models, methods and tools for CPUs and memories silicon debug and validation aiming to detect and locate hard-to-detect design bugs that escape pre-silicon, simulation-based verification. Our methods aim to improve the coverage of the silicon debug process (and thus its bug detection capability) while reducing significantly the time of the process.
We deliver methods and tools for the evaluation of computing systems reliability for different types of models (transients or permanents) and for all major hardware components including CPUs, GPUs and memories. The main focus is on the speed of the reliability evaluation and its accuracy. We work at the microarchitecture level, the software level and the RT level.
We investigate the margins of modern computing systems hardware to reveal the potential of energy and power savings when they operate beyond nominal conditions of voltage, frequency and refresh rates. We characterize the variation among different chips, different cores within chips and different workloads regarding their design margins, aiming to predict safe and energy-efficient operation points of modern hardware.
We design hardware-based and software-based methods for the detection and tolerance of transient and permanent faults in the hardware components of computing systems. We provide solutions for CPUs, GPUs and memories. The main focus is the error coverage of the methods as well as the minimization of their cost in terms of system performance, energy/power and hardware area.