Energy Efficiency

Lab’s paper ACCEPTED @ IEEE TDMR

G. Papadimitriou, A. Chatzidimitriou, D. Gizopoulos, V. J. Reddi, J. Leng, B. Salami, O. S. Unsal, and A. C. Kestelman, “Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins”, IEEE Transactions on Device and Materials Reliability (IEEE TDMR), April 2020.

Lab’s paper ACCEPTED @ IEEE ISPASS 2019

Assessing the Effects of Low Voltage in Branch Prediction Units, A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, S. Ganapathy, and J. Kalamatianos, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2019), Madison, Wisconsin, USA, March 2019.

MICRO-51 Tutorial for Energy Efficient Computing

Energy Efficient Computing in Multicore CPUs: Design Margins and Variability Sunday, October 21 2018, Fukuoka, Japan Afternoon tutorial held in conjunction with 51st IEEE/ACM International Symposium on Microarchitecture (MICRO 2018) Organizers/Presenters: Dimitris Gizopoulos, George Papadimitriou, Athanasios Chatzidimitriou (University of Athens) Tutorial Summary Conservative design margins in modern multicore CPU chips aim to guarantee correct...

2 CAL’s papers ACCEPTED @ IEEE IOLTS 2018 & IEEE/IFIP DSN 2018

A. Chatzidimitriou, G. Papadimitriou, D. Gizopoulos, “HealthLog Monitor: A Flexible System-Monitoring Linux Service, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), Costa Brava, Spain, July 2018. K. Tovletoglou, L. Mukhanov, G. Karakonstantis, A. Chatzidimitriou, G. Papadimitriou, M. Kaliorakis, D. Gizopoulos, Z. Hadjilambrou, Y. Sazeides, A. Lampropulos, S. Das, P. Vo,...

ISCA-45 Tutorial for Energy Efficient Computing

Energy Efficient Computing in Multicore CPUs: Design Margins and Variability Sunday, 3 June 2018, Los Angeles, California, USA Morning tutorial held in conjunction with 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018) Organizers/Presenters: Dimitris Gizopoulos, George Papadimitriou, Athanasios Chatzidimitriou (University of Athens) Tutorial Summary Conservative design margins in modern multicore CPU chips aim...

Lab’s paper ACCEPTED @ IEEE ISPASS 2018

“Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs”, G. Papadimitriou, A. Chatzidimitriou, M. Kaliorakis, Y. Vastakis, D. Gizopoulos, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2018), Belfast, Northern Ireland, United Kingdom, April 2018.