Microarchitecture Level Reliability Assessment: Throughput and Accuracy Sunday, 15 October 2017, Boston, MA, USA Morning tutorial held in conjunction with MICRO 2017 Tutorial Summary Early assessment of the vulnerability of microprocessor components to hardware faults can drive effective protection decisions. Microarchitecture-level simulators are employed for such early assessments and can deliver reliability reports for...
“RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU”, A.Chatzidimitriou, M.Kaliorakis, D.Gizopoulos, M.Iacaruso, M.Pipponzi, R.Mariani, S.Di Carlo, IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), Denver, CO, USA, June 2017.
“MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment”, M.Kaliorakis, D.Gizopoulos, R.Canal, A.Gonzalez, ACM/IEEE International Symposium on Computer Architecture (ISCA 2017), Toronto, Canada, June 2017